The present invention relates to a layout design apparatus of semiconductor IC device, a layout design system of semiconductor IC device, a layout design method of semiconductor IC device, and a computer-readable recording medium on which programs for allowing a computer to execute respective means in the system or respective steps in the method are recorded.
Generally, a semiconductor IC device has a sequential circuit such as a flip-flop which is operated in synchronization with a clock. A clock signal supplied from inside or outside the IC chip generally passes through several buffers so as to reach the flip-flop. For this reason, the time required for the clock signal to reach the respective flip-flop circuit, namely, the delay is occasionally different from each other per flip-flop circuit, and this is called as clock skew. When the clock skew is large, there is a possibility that the circuits malfunction. As a result, it is necessary to reduce the clock skew as small as possible.
Conventionally, in the layout design of the semiconductor IC device, wires are automatically distributed between buffer cells and between the buffer cells and flip-flops using Design Automation. In general, Design Automation generates a clock tree such that the clock skew is minimum in a layout block (hereinafter, block). However, in the case of a hierarchical layout having a plurality of blocks, clock skew between the blocks becomes a problem. In order to set the clock skew between the blocks to minimum, there is known a method of setting the delay of respective blocks same to and also make the wiring lengths between terminals to which a clock signal is supplied and the blocks same.
However, in the above conventional method, there is a disadvantage that a degree of freedom of the layout design is reduced, and there is a problem that workload and time are required because a designer makes the design manually.
It is an object of the present invention to provide a layout design system of semiconductor IC device and a layout design method of semiconductor IC device which are capable of automatically designing a hierarchical layout having a plurality of blocks so that clock skew between the blocks becomes as small as possible, and relates to a computer-readable recording medium on which programs for allowing a computer to execute respective means in the system or respective steps in the method are recorded.
In order to achieve the above object, the present invention designs a layout of a semiconductor IC device according to the following steps. After a floor plan and cell layout in each of blocks are designed, a clock tree is generated in the block at the lower level of hierarchy so that clock skew in each of the blocks becomes minimum.
Then, a placement position of a clock buffer (root clock driver) to be a basis of a clock signal in each of the blocks and information about an area where cells can be placed are given to the higher level block, and an average delay value of delay values from the clock buffer to a distal buffer is obtained for each of the blocks. A clock tree is generated in the block at the higher level of hierarchy based on these information so that the clock skew between the blocks becomes minimum.
In the case where a buffer, which is newly generated at the time of generating the clock tree in the block at the higher level of hierarchy, exists, a placement position of the generated buffer is returned to the block at the lower level of hierarchy so as to be adjusted based on the cell layout of the corresponding block. A wire is distributed in each of the block at the block at the lower -level of hierarchy, and a wire is distributed between the blocks at the block at the higher level of hierarchy.
In another manner, after the clock tree is generated at the block at the higher level of hierarchy so that the clock skew between the blocks becomes minimum, in the case where a buffer which is newly generated at the time of generating the clock tree exists, the cell layout in each of the blocks is designed by taking the placement position of the generated buffer into consideration. Thereafter, the clock tree in each of the blocks is designed at the block at the lower level of hierarchy, and a wire may be distributed.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.